This invention relates to a power supply controlling circuit and a power supply controlling method, and more particularly to a power supply controlling circuit and a power supply controlling method wherein the frequency of a system clock signal and the power supply voltage to be supplied to a module which forms, for example, a one-chip semiconductor circuit or a like circuit can be continuously varied to reduce the power consumption of the module.
FIG. 6 shows a construction of an example of a conventional semiconductor circuit.
Referring to FIG. 6, the semiconductor circuit shown includes a buffer 2, a pair of modules 4 and 6, a controller 21 and a pair of AND gates 22 and 23, which are all included in one chip, and performs predetermined processing in accordance with a system clock signal generated by an external clock generator 1.
In particular, the clock generator 1 generates a clock signal of a predetermined fixed frequency. This clock signal is supplied as a system clock signal to the module 4 through the buffer 2 and the AND gate 22 and also to the module 6 through the buffer 2 and the AND gate 23.
The module 4 receives data supplied thereto from the outside, and performs predetermined processing in synchronism with the system clock signal supplied through the AND gate 22 and outputs data of a result of the processing to the module 6. The module 6 performs predetermined processing for the data outputted from the module 4 in synchronism with the system clock signal supplied thereto through the AND gate 23 and outputs data obtained as a result of the processing, similarly to the module 4.
Meanwhile, the controller 21 receives a control signal (application control signal) for controlling on/off of supply of the system clock signal to the modules 4 and 6. The control signal is supplied from a predetermined application (which may be any of hardware and software) The controller 21 outputs the L or H levels to the AND gates 22 and 23 in accordance with the control signal.
In particular, the controller 21 normally outputs the H level to the AND gates 22 and 23 so that the system clock signal is supplied to the modules 4 and 6 through the AND gates 22 and 23, respectively. Meanwhile, for example, on the application side, a processing state of the module 6 which is the following stage one of the modules 4 and 6 is predicted or detected by some method, and if data to be processed has not arrived at the module 6, then a control signal indicating that supply of the clock signal to the module 6 should be stopped is supplied to the controller 21. In this instance, the controller 21 outputs the L level to the AND gate 23, and consequently, supply of the system clock signal to the module 6 is stopped.
Thereafter, if it is detected by the application side that data is inputted to the module 6, then a control signal indicating that supply of the clock signal to the module 6 should be started is supplied to the controller 21. In response to the control signal, the controller 21 outputs the H level to the AND gate 23, and consequently, supply of the system clock signal to the module 6 is started.
Also with regard to supply of the clock signal to the module 4, on/off control similar to that to the module 6 is performed by varying the input level to the AND gate 22.
Where such on/off control of supply of the system clock signal as described above is performed, the modules do not operate while supply of the system clock signals to them in off. Consequently, the power consumption of the semiconductor circuit can be reduced when compared with an alternative case wherein the system clock signal is supplied incessantly.
However, it is demanded in recent years to further reduce the power consumption of a semiconductor circuit.
It is an object of the present invention to provide a power supply controlling circuit and a power supply controlling method by which further reduction of the power consumption can be achieved.
In order to attain the object described above, according to an aspect of the present invention, there is provided a power supply controlling circuit for controlling a power supply voltage to be supplied to a module which performs predetermined processing in synchronism with a predetermined system clock signal, comprising detection means for detecting a processing state of the module and control means for continuously varying the frequency of the system clock signal and the power supply voltage in response to a result of the detection of the detection means.
In the power supply controlling circuit, the detection means detects a processing state of the module, and the control means continuously varies the frequency of the system clock signal and the power supply voltage in response to a result of the detection of the detection means.
According to another aspect of the present invention, there is provided a power supply controlling method for controlling a power supply voltage to be supplied to a module which performs predetermined processing in synchronism with a predetermined system clock signal, comprising the steps of detecting a processing state of the module, and continuously varying the frequency of the system clock signal and the power supply voltage in response to a result of the detection of the processing state of the module.
In the power supply controlling method, a processing state of the module is detected, and the frequency of the system clock signal and the power supply voltage are continuously varied in response to a result of the detection of the detection means.
With the power supply controlling apparatus and the power supply controlling method, a processing state of the module is detected, and the frequency of the system clock signal and the power supply voltage are continuously varied in response to a result of the detection of the detection means. Accordingly, the power consumption of the module can be controlled lower than ever.